Resume
Education
Graduation: June 2025 (Graduated)University of California, Santa Cruz
Bachelor of Science in Computer Engineering
Relevant coursework
Computer NetworksData Structures and AlgorithmsArtificial IntelligenceEmbedded System DesignOperating SystemsPythonC/C++Java
Skills
Core
NetworkingPythonJavaC/C++DebuggingHardware/Software Co-Design
Tools / Frameworks / Hardware
WiresharkLinuxMininetPOX ControllerRoutersFirewallsLaTeXAvigilonAWSGraphQLGit
Achievements
- Dean’s Honor Roll (Spring 2025)
Experience
Network Support Technician
Qovo Solutions
Winter 2024 – Spring 2025
Morgan Hill, CA
- Installed, configured, and supported enterprise-grade Avigilon IP camera systems across commercial sites, ensuring optimal coverage and network integration.
- Diagnosed complex network issues using Wireshark and Avigilon Control Center, resolving connectivity, performance, and routing problems in client environments.
- Managed IP configurations, VLAN setup, and port-forwarding rules to ensure secure remote access and scalability on Linux systems.
- Independently implemented a software-defined router using POX and Mininet for real-world enterprise network environments.
- Developed and enforced advanced traffic control policies based on TCP, UDP, and ICMP protocols to restrict or permit communication between segmented subnets.
- Validated firewall and routing logic through automated and live demonstrations, showcasing robust handling of protocol-specific behavior and access controls.
Backend Developer
Slugmatch Alumni Platform (UC Santa Cruz Alumni Association)
Fall 2024
Santa Cruz, CA
- Architected and implemented the backend for Slugmatch, a full-featured alumni engagement platform aimed at bringing alumni, students, and staff together.
- Designed and integrated REST and GraphQL APIs to support event listings, networking features, and real-time matchmaking.
- Utilized AWS services (Lambda, DynamoDB, S3, AppSync) to build a scalable, serverless architecture with seamless frontend integration via React.
- Implemented user authentication, access controls, invite handling, and robust data syncing to support community engagement goals.
- Ensured high reliability by writing unit tests, performance tuning GraphQL resolvers, and optimizing database access patterns, reducing query latency by ~40%.
Projects
Floating Point Adder Optimization
SystemVerilogYosysnextpnrVerilatorPythoniCEBreaker
- Optimized an IEEE-754 combinational floating-point adder to improve FPGA timing performance by 4×.
- Increased operating frequency by 312% (from 8 MHz to 33 MHz) through pipeline tuning and logic restructuring.
- Used Verilator and DPI-C for fuzz testing, correctness validation, and performance benchmarking.
- Synthesized design with Yosys/nextpnr toolchain for iCEBreaker FPGA; validated via UART and Python scripting.
FPGA Hardware Labs
SystemVerilogVerilator
- Designed FIFO, RAM-based buffers, and ready/valid pipelines in SystemVerilog.
- Built and tested pipelined adder/multiplier/MAC units with timing-aware design practices.
- Verified functionality using Verilator-based simulation and maintained reusable source code for regression testing.
FPGA-Based Audio Tuner
iCEBreaker FPGASystemVerilogDSPMAC pipeline
- Designed and implemented a real-time audio tuner on the iCEBreaker FPGA.
- Developed a Multiply-Accumulate (MAC) pipeline to compute inner products between samples and reference signals.
- Generated sinusoids for multiple musical notes (A–G) to detect dominant frequencies with ±1 Hz precision.
- Optimized signal processing pipeline using hardware parallelism in an R&D exploration of real-time pitch detection.
ESP32-C3 Bluetooth Mouse
ESP32-C3ESP-IDFBluetooth HIDI2C
- Built a wireless Bluetooth HID mouse using the ESP32-C3 microcontroller for cursor emulation.
- Interfaced an ICM-42670-P accelerometer over I2C and leveraged the ESP-IDF Bluetooth stack for reliable cross-platform performance.
Software-Defined Networking & OpenFlow Firewall (POX)
PythonPOXMininetOpenFlow 1.3
- Wrote a custom firewall controller in Python using POX to manage flow rules in a simulated OpenFlow network.
- Developed rule logic to enforce ICMP, TCP, and UDP access control policies across hosts, IoT devices, and servers.
- Implemented dynamic flow handling for packet-in events and flow modification using OpenFlow 1.3.
- Extended the firewall to detect and block simulated DoS attacks by inspecting protocol behavior and adapting rule sets.
- Validated controller performance through interactive Python-based tests and Mininet simulations.
KVS Cache System
CValgrindclang-format
- Developed a high-performance key-value store in C with an in-memory caching layer on top of a file-based backend.
- Implemented FIFO, Clock, and LRU eviction policies using distinct data structures and algorithms.
- Designed and tested GET, SET, and FLUSH operations with policy-specific behavior using pointer-based memory management.
- Used Valgrind and clang-format to ensure memory safety and maintain code quality.
svAi (SystemVerilog Assistant)
TauriRustReactTypeScriptMonaco EditorSystemVerilogVerilatorGTKWaveMSYS2Ollama
- Built a lightweight Windows desktop IDE for SystemVerilog: edit → lint → build → run → view waveforms.
- Implemented a robust Verilator + make pipeline (via MSYS2 bash) with error parsing, quick navigation, and safe prompts for unsaved files.
- Integrated GTKWave for FST waveform viewing; added project config (.svlab.json) and filelist management (files.f) for reproducible builds.
- Developed an AI-assisted edit workflow (local Ollama or API) supporting safe file ops (create/write/edit), multi-file review/apply, and patch previews.