Portfolio

Projects

Selected work. Use the toggle to switch between hardware and software projects.

Floating Point Adder Optimization

SystemVerilogYosysnextpnrVerilatorPythoniCEBreaker
  • Optimized an IEEE-754 combinational floating-point adder to improve FPGA timing performance by 4×.
  • Increased operating frequency by 312% (from 8 MHz to 33 MHz) through pipeline tuning and logic restructuring.
  • Used Verilator and DPI-C for fuzz testing, correctness validation, and performance benchmarking.
  • Synthesized design with Yosys/nextpnr toolchain for iCEBreaker FPGA; validated via UART and Python scripting.

FPGA Hardware Labs

SystemVerilogVerilator
  • Designed FIFO, RAM-based buffers, and ready/valid pipelines in SystemVerilog.
  • Built and tested pipelined adder/multiplier/MAC units with timing-aware design practices.
  • Verified functionality using Verilator-based simulation and maintained reusable source code for regression testing.

FPGA-Based Audio Tuner

iCEBreaker FPGASystemVerilogDSPMAC pipeline
  • Designed and implemented a real-time audio tuner on the iCEBreaker FPGA.
  • Developed a Multiply-Accumulate (MAC) pipeline to compute inner products between samples and reference signals.
  • Generated sinusoids for multiple musical notes (A–G) to detect dominant frequencies with ±1 Hz precision.
  • Optimized signal processing pipeline using hardware parallelism in an R&D exploration of real-time pitch detection.

ESP32-C3 Bluetooth Mouse

ESP32-C3ESP-IDFBluetooth HIDI2C
  • Built a wireless Bluetooth HID mouse using the ESP32-C3 microcontroller for cursor emulation.
  • Interfaced an ICM-42670-P accelerometer over I2C and leveraged the ESP-IDF Bluetooth stack for reliable cross-platform performance.

svAi (SystemVerilog Assistant)

TauriRustReactTypeScriptMonaco EditorSystemVerilogVerilatorGTKWaveMSYS2Ollama
  • Built a lightweight Windows desktop IDE for SystemVerilog: edit → lint → build → run → view waveforms.
  • Implemented a robust Verilator + make pipeline (via MSYS2 bash) with error parsing, quick navigation, and safe prompts for unsaved files.
  • Integrated GTKWave for FST waveform viewing; added project config (.svlab.json) and filelist management (files.f) for reproducible builds.
  • Developed an AI-assisted edit workflow (local Ollama or API) supporting safe file ops (create/write/edit), multi-file review/apply, and patch previews.